One operation frequently employed in the production of semiconductors is an etching operation. In an etching operation, one or more materials are partly or wholly removed from a partially fabricated integrated circuit. Plasma etching is often used, especially where the geometries involved are small, high aspect ratios are used, or precise pattern transfer is needed. Typically, a plasma contains electrons, ions and radicals. The radicals and ions interact with a substrate to etch features, surfaces and materials on the substrate.
As device dimension shrink, plasma etching processes need to be increasingly precise and uniform in order to produce quality products. One driving factor for decreasing device dimensions is the push to provide more devices per substrate. A related factor is the move from planar to 3D transistor structures (e.g., FinFET gate structures for logic devices) and advanced memory structures (e.g., Magnetoresistive Random Access Memory (MRAM) and Resistive Random Access Memory (ReRAM)). In order to achieve such precise and uniform processes, different processes must be optimized based on several relevant factors (e.g., the application for which the device will be used, the chemistry involved, the sensitivity of the substrate, etc.). Among other factors, a few important variables that may be optimized in an etching process include the flux of ions to a substrate, the flux of radicals to a substrate, and the related ratio between these two fluxes.
Because different processes are optimized in different ways, an apparatus which is suitable for a first etching process may not be suitable for a second etching process. Due in part to limited space in processing facilities, as well as the cost of semiconductor fabrication equipment, it is desirable for a semiconductor fabrication apparatus to be able to provide a wide range of processing conditions over a substrate. Further, it may be desirable for a semiconductor apparatus to be able to provide a wide range of processing conditions over different parts of a substrate during processing to combat certain geometric non-uniformities. This consideration is especially important where large substrates (e.g., 300 mm and especially 450 mm diameter) are being processed, as the geometric non-uniformities are exacerbated in such large work pieces. In this way, a single apparatus may be used for many different applications to achieve uniform results. The techniques described herein are especially useful for performing multi-step etch processes such as those associated with FinFET structures and back-end-of-line (BEOL) processing such as certain dual Damascene processes, particularly when performed on large substrates. The disclosed embodiments may be particularly useful in certain advanced technology nodes such as the 40 nm node, the 10 nm node, and the 7 nm node.